built with concourse

OVERVIEW

Each example uses iverilog to simulate and GTKWave to view the waveform. I also used Xilinx Vivado to synthesize and program these verilog examples on a Digilent ARTY-S7 FPGA development board.

I declare my ports as follows because that’s what the synthesis tools want. Who am I to argue.

    module NAME (
        input             a,     // Input A
        input       [7:0] b,     // Input B
        output reg  [3:0] y);    // Output Y

Also, I would stay away from asynchronous design. It can have problems when you synthesize to an FPGA.


    // DO THIS
    always @(posedge clk) begin
        if (~reset) begin
            ...

    // NOT THIS
    always @(posedge clk or negedge reset) begin

Each example has the following 4 files,

The artifacts created are,

Where the testbench structure is,

testbench-structure.jpg

BASIC CODE

COMBINATIONAL LOGIC

FPGA DEVELOPMENT BOARDS

SEQUENTIAL LOGIC

SYSTEMS